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#	Item
771	Support Workshop BW Feature Pack SAP AG Berlin, June 2007 Add to Reading List Source URL: maxdb.sap.com Language: English - Date: 2007-12-05 10:15:47 Computer cluster CPU cache Computing Database index Databases
772	DECchip[removed]Evaluation Board User’s Guide Order Number: EC–N0351–72 Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:02:08 Alpha 21064 Dynamic random-access memory DEC Alpha Computer workstations SIMM CPU cache DEC 4000 AXP DEC 7000/10000 AXP Computer hardware Computing Computer memory
773	BulkSMT: Designing SMT Processors for Atomic-Block Execution∗ Xuehai Qian, Benjamin Sahelices and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Abstract Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2012-01-18 11:44:30 Computer architecture Central processing unit Parallel computing Microprocessors CPU cache Simultaneous multithreading Multithreading Computing Computer hardware Threads
774	Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation ˜ ´ Garzar´an, Milos Prvulovic, V´ıctor Vinals Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-09-29 23:57:21 Central processing unit Computer memory CPU cache Cache Parallel computing Hazard Superscalar Stack Computing Computer hardware Computer architecture
775	IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING (TDSC) 1 Using Register Lifetime Predictions to Protect Register Files Against Soft Errors Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:16:16 Central processing unit Computer memory Register renaming CPU cache Register file Branch predictor Parity bit Processor register 64-bit Computer architecture Computer hardware Computing
776	CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-27 00:10:17 Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering
777	,&6¶3URJUDPDWDODQFH Add to Reading List Source URL: www.ecse.monash.edu.au Language: English* - Date: 2002-06-13 21:40:34 Semiconductor companies Concurrent computing FLOPS University of Illinois at Urbana–Champaign CPU cache Supercomputer IBM Intel Universal Product Code Computing Computer hardware Parallel computing
778	BulkSC: Bulk Enforcement of Sequential Consistency Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-07 18:09:31 Computer architecture Central processing unit CPU cache Cache Parallel computing C dynamic memory allocation Microarchitecture Advanced Micro Devices Transactional memory Computer hardware Computer memory Computing
779	Design Note: Target Considerations for Coldfire † Jonathan S. Shapiro, Ph.D. The EROS Group, LLC Dec 1, 2007 Abstract Add to Reading List Source URL: www.coyotos.org Language: English - Date: 2014-08-13 02:10:11 Virtual memory Computing Computer memory CPU cache Cache Page table Page Microkernel Kernel Computer architecture Central processing unit Computer hardware

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